Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), field programmable systems on a chip (FPSCs), or other types of programmable devices) may be configured with various user designs to implement desired functionality. Typically, the user designs are synthesized and mapped into configurable resources (e.g., programmable logic gates, look-up tables (LUTs), embedded hardware, or other types of resources) and interconnections available in particular PLDs. Physical placement and routing for the synthesized and mapped user designs may then be determined to generate configuration data for the particular PLDs.
Two primary types of configurable resources of a PLD include programmable logic blocks (PLBs) and routing resources. The logic blocks typically include a number of logic cells each containing a LUT and a register with some additional logic. The routing resources flexibly connect the logic blocks and/or cells to one another and can constitute greater than 65% of the area of the PLD, can consume most of the available power, and can take up most of a timing budget associated with a particular user design. In some cases, greater than 80% of the configuration bit cells (e.g., programmable memory) are used for routing. As such, routing limitations restrict PLB utilization. PLB utilization can be improved by increasing the amount of available routing resources, but such increases consume more area.
Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.